High speed electronic digital computers of the type produced by Cray Research, Inc., the assignee hereof, typically require short length electrical connections between various electrical cards and chips. Timing problems between electrical signals can result from electrical signals passing through different conductor path lengths. Shorter length electrical connections introduce fewer timing problems between signals within the high speed digital computer. The shorter path lengths also provide better electrical performance when compared to longer path length conductors.
The trend in electronic packaging for a long time now has been to pack more electronics, such as transistors, onto a single substrate. Some microprocessors, for example, include 10,000,000 transistors in a 1.5 inch square substrate. Now what used to fit on multiple chips can be made to fit on a single substrate. However, yields limit the maximum size of an integrated circuit (IC). In other words, yields generally drop drastically at some point when making a large die. At the drastic yield dropping point, the cost per part skyrockets. It is generally desirable to pack logic within smaller and smaller spaces. This, however, must be balanced by an optimization of cost/part. Chips can be fabricated and packaged singly (single chip modules or SCMs) or with multiple chips attached to a common substrate (multi-chip modules or MCMs). Placing more electronics onto a single substrate produces shorter length electrical paths which is desirable from the standpoint of designing a computer. Shorter path lengths lessen timing problems for various signals.
Even though great strides have been made in packing more and more electronics and chips onto one substrate, the modules are still part of a multilevel interconnect system in most applications. Although MCMs are still not widely used and have not displaced other modules in some computer architectures, it is necessary to have many multiple chip modules and single chip modules in electrical communication with one another to effect an application capability to a system user. To achieve this, single chip modules and multiple chip modules are currently mounted onto a first printed circuit board. Several more of the many single chip modules and multiple chip modules are mounted onto a second printed circuit board. Similar to optimum yield-cost for integrated circuits, systems are optimally partitioned into printed circuit boards populated with appropriate chips. All the printed circuit boards are in turn connected to a back plane. The back plane is a planar board with a number of edge connectors thereon. Each edge type connector on the back plane grips the edge of a circuit board having multi-chip or single chip modules thereon. The edge connectors of the back plane receive the edges of the circuit boards. The back plane typically provides a connection to the data bus and command bus of the computer. The back plane could itself be another circuit board having edge type connectors connected to yet another back plane. In addition, in some systems single or multi-chip modules are mounted on the back plane(s) themselves.
The problem with such a system is that when a signal must pass from one module on a first printed circuit board to another module on a second circuit board, the signal path length becomes long, thereby limiting propagation speed. This is especially pronounced in a supercomputer environment where large amounts of data or commands are being moved from one module to another module. Each time the signal passes from one level of packaging to another level of packaging, such as from the printed circuit board to the back plane, the signal is also slowed down since the electrical path will be longer.
Other problems limit the capability of such a system. Increasing the number of interconnects, reduces the reliability of the system, particularly when `hard attaches` (such as commonly used BGA or CGA) interconnect materials having different coefficients of thermal expansion (such as SCM or MCM substrates connected to printed circuit boards). Also, the current system of mounting the modules on printed circuit boards and then, in turn, mounting the printed circuit boards to a back plane uses a large amount of space. In addition, such systems are also difficult to cool.
There is a need for a system and method to overcome many of these current problems. A system and method needs to provide space savings and shorter path lengths. Such a method and system would reduce timing problems that result from delayed signals. The system and method should cut down on the number of layers necessary to interconnect a number of multiple module chips or single module chips. The system should also be easy to assemble and provide for good electrical contact to be made. In addition, the system and method should provide access to the individual modules and provide adequate access for cooling the individual modules as it is required from the designer's standpoint.